Comparison of x86 and x86-64 Architectures: Register System Differences
32-bit (x86) vs. 64-bit (x86-64) Register Comparison:
| Functional Category | x86 (32-bit) | x86-64 (64-bit) | Extension Features |
|---|---|---|---|
| General-Purpose Registers | EAX/EBX/ECX/EDX | RAX/RBX/RCX/RDX | Increased from 8 to 16 general-purpose registers |
| Pointer Registers | ESP/EBP | RSP/RBP | Added R8–R15 |
| System Registers | EFLAGS | RFLAGS | Added control register CR8 |
| Segment Registers | CS/DS/SS/ES | CS/DS/SS/ES/FS/GS | Extended usage of FS/GS |
64-bit Addressing Advantage Example:
; x86-64 can directly access larger memory space
mov rax, [0xFFFFFFFFFFFFFFFF] ; Valid 64-bit address access
; Equivalent operation on x86 requires segmentation mechanism
mov eax, [fs:0x7FFF0000] ; Relies on segment base address
64-bit Specific Instructions:
SWAPGS: Quickly switch kernel/user GS base addressesSYSCALL/SYSRET: Fast system callsMOVSXD: Sign-extend 32-bit to 64-bit
Differences in Compatibility Mode:
; x86-64 running 32-bit code requires mode switching
mov eax, 0x23 ; Set CS.L=1, CS.D=0 (32-bit mode)
mov cr0, eax
jmp 0x33:.L32bit_code
.L32bit_code:
mov eax, 1 ; Now operating in 32-bit operand size
ARM Architecture Assembly
AArch32 (ARMv7) Basics
Core Register Set:
- R0–R15: General-purpose registers (includes PC/SP/LR)
- CPSR: Current Program Status Register
- SPSR: Saved Program Status Register
Typical Instruction Examples:
; ARMv7 data processing instructions
MOV R0, #0x10 ; Load immediate value
LDR R1, [R2, #4] ; Base + offset addressing
ADD R3, R1, R2 ; Addition
BX LR ; Subroutine return
Conditional Execution Feature:
CMP R0, R1
MOVEQ R2, #1 ; Execute only if Z=1 (equal)
MOVNE R2, #0 ; Execute only if Z=0 (not equal)
AArch64 (ARMv8) Evolution
64-bit Register Mapping:
- X0–X30: 64-bit general-purpose registers (correspond to ARMv7’s R0–R30)
- W0–W30: 32-bit views (lower 32 bits)
- SP/XZR: Stack pointer / Zero register
New Instruction Examples:
; AArch64-specific instructions
LDXR X0, [X1] ; Load exclusive (atomic operation)
STXR W2, X0, [X1] ; Store exclusive
MADD X3, X4, X5, X6 ; Multiply-add: X3 = X4*X5 + X6
System Call Differences:
; ARMv7 system call (via SWI)
MOV R7, #4 ; syscall number
SWI 0
; AArch64 system call (via SVC)
MOV X8, #64 ; syscall number
SVC #0
RISC-V Architecture Assembly
RV32I Base Instruction Set
Core Registers:
- x0–x31: 32 general-purpose registers (x0 is hardwired to 0)
- pc: Program counter
Basic Instruction Examples:
; RV32I integer instructions
ADDI x5, x6, 42 ; Add immediate
LW x7, 8(x8) ; Load word
SW x9, 12(x10) ; Store word
BEQ x11, x12, label ; Conditional branch
CSR Access Instructions:
CSRRW x1, mstatus, x2 ; Read-modify-write Control and Status Register
CSRRSI x3, mtvec, 4 ; CSR read with bit set
RV64I Extension
64-bit Operation Instructions:
ADDIW x10, x11, 100 ; Sign-extended immediate addition
LD x12, 16(x13) ; Load doubleword (64-bit)
SD x14, 24(x15) ; Store doubleword
SLLI x16, x17, 32 ; Immediate logical left shift (64-bit)
Privilege Mode Differences:
- M-mode (Machine mode): Highest privilege level
- S-mode (Supervisor mode): Used by operating systems
- U-mode (User mode): For applications
MIPS Architecture Assembly
MIPS32 Basics
Register Conventions:
$0–$31: General-purpose registers ($0is hardwired to 0)$a0–$a3: Function arguments$v0–$v1: Return values$ra: Return address
Typical Instructions:
; MIPS32 data processing
ADDI $t0, $zero, 100 ; $t0 = 100
LW $t1, 0($t2) ; Load from memory
SW $t3, 4($t4) ; Store to memory
BEQ $t5, $t6, label ; Conditional branch
Delay Slot Feature:
J label ; Jump instruction
NOP ; Delay slot must be filled
; Or use delay slot for useful work:
ADD $t0, $t1, $t2 ; Executed in delay slot
MIPS64 Extension
64-bit Operation Example:
DADDI $t0, $zero, 0x100000000 ; 64-bit immediate addition
LD $t1, 8($t2) ; Load doubleword (64-bit)
SD $t3, 16($t4) ; Store doubleword
DSLL $t5, $t6, 32 ; 64-bit logical left shiftCP0 Coprocessor:
MFC0 $t0, $12 ; Read status register
MTFC0 $t1, $13 ; Write cause register
Cross-Compilation Techniques
Toolchain Configuration
GCC Cross-Compilation Examples:
# x86 → ARM cross-compilation
arm-linux-gnueabihf-as -o prog.o prog.s
arm-linux-gnueabihf-ld -o prog prog.o
# RISC-V toolchain
riscv64-unknown-elf-as -march=rv64gc -o prog.o prog.s
riscv64-unknown-elf-ld -T linker.ld -o prog prog.o
Handling Assembler Directive Differences:
// Conditional compilation example (via macros)
#ifdef __x86_64__
mov rax, 1
#elif defined(__arm__)
mov w0, #1
#elif defined(__riscv__)
li a0, 1
#endif
Custom Linker Scripts
RISC-V Linker Script Example:
ENTRY(_start)
MEMORY {
RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 128K
}
SECTIONS {
.text : { *(.text.boot) *(.text .text.*) } > RAM
.data : { *(.data) } > RAM
.bss : { *(.bss) } > RAM
}
Platform-Specific Optimization
Instruction Scheduling Strategies
x86-64 Pipeline Optimization:
; Avoid data dependency stalls
mov rax, [mem1]
mov rbx, [mem2] ; Independent memory access
add rax, rbx ; No RAW (Read-After-Write) dependency
ARM Pipeline Optimization:
; Leverage instruction-level parallelism
LDR R0, [R1], #4 ; Prefetch next instruction
ADD R2, R0, R3 ; Execute in parallel
STR R2, [R4], #4
Memory Model Differences
x86-TSO Memory Model:
- Write operations automatically become globally visible
- No explicit memory barriers required
ARM/POWER Weak Memory Model:
; ARM requires explicit memory barriers
LDR R0, [R1]
DMB ISH ; Data Memory Barrier
STR R0, [R2]
Debugging and Disassembly
Cross-Platform Debugging Tools
GDB Multi-Architecture Support:
# Debug ARM program
arm-linux-gnueabihf-gdb ./program
# Remote debugging
target remote :1234
Disassembly Comparison Examples:
# x86-64 disassembly
objdump -d -M intel program
# ARM disassembly
arm-linux-gnueabihf-objdump -d -M force-thumb program
# RISC-V disassembly
riscv64-unknown-elf-objdump -d -M numeric program
By mastering these cross-platform assembly techniques, developers can:
- Develop cross-platform low-level software
- Analyze multi-architecture binary programs
- Implement high-performance computing libraries
- Build security research toolchains
- Contribute to open-source hardware development
